1. Field of the Invention
The present invention relates to a semiconductor storage device, and particularly to a divided-word-line type semiconductor storage device and electronic equipment using such a semiconductor storage device.
2. Description of the Prior Art
Such a semiconductor storage device is known, for example, from Japanese Patent Laid-Open Nos. 62-75996 and 64-64192.
One example of these semiconductor storage devices is shown in FIGS. 13A, 13B and 14. FIG. 13A is a schematic block diagram of a known divided-word-line type semiconductor storage device, while FIG. 13B is a block diagram illustrating, in an enlarged scale, a part of the memory cell area in FIG. 13A. FIG. 14 is a circuit diagram illustrating a part of the main row decoder 402 in the semiconductor storage device of FIG. 13A. The known related art will be described with reference to these figures.
Referring now to FIG. 13A, a main row decoder 402 is disposed at the center of parallelly disposed memory cell blocks 400. A sub row decoder 404 is provided for each memory cell block 400. One of main word lines 406 is selected by the main row decoder 402 while one of sub word lines 408 depending on one selected main word line 406 is selected by the corresponding sub row decoder 404.
A mechanism for selecting a main word line 406 through the main row decoder 402 will be described in connection with FIG. 14. FIG. 14 illustrates a system having a NOR gate NOR1 and main word line drivers DRR and DRL each of which is constructed by two inverters connected in series with each other. The input of the NOR gate NOR1 is connected to main-row address signal lines MRAL.
Only when all of the signal lines connected to the input of the NOR gate NOR1 in the main row address signal lines MRAL are in low level (which will be referred simply to "L"), the output of the NOR gate NOR1 becomes high level (which will be referred simply to "H") to activate the main word lines 406. If any one of the signal lines connected to the input of the NOR gate NOR1 in the lines MRAL is in "H", the output of the NOR gate NOR1 becomes "L". Therefore, the main word lines 406 will be in "H" under their selected state and in "L" under their non-selected state.
Next, a mechanism for selecting a sub word line 408 through the sub row decoder 404 will be described with reference to FIG. 13B.
Referring to FIG. 13B, each memory cell MC disposed in each of the memory cell blocks 400 is connected to bit lines BL and /BL for data input/output as well as one of the sub word lines 408. Each of the bit lines BL and /BL is connected at one end to a pre-charge circuit PCC for charging the bit lines BL and /BL when the corresponding memory cell MC is not selected. The input of the sub row decoder 404 is connected to a line branched from the main word line 406 and sub row address signal lines SRAL.
When it is desired to select one of the sub word lines 408 depending on the activated main word line 406, the sub word line 408 is activated by an address signal supplied from the sub row address signal lines SRAL.
At this time, the potential level in the bit lines BL and /BL has previously been in "H" level by the pre-charge circuit PCC under the non-selected state. Pre-charging is one method for improvement in speed and stability, having an advantage that a time to charge a capacitance of a bit line in a data writing/reading operation can be reduced. Thus, one of the memory cells MC will be selected by activating the bit lines BL and /BL and the sub word line 408.
From the viewpoint of high-integration, the divided-word-line type semiconductor storage device is generally constructed to have different wiring layers respectively including sub word lines, main word lines and bit lines, when the bit lines intersect the main word lines. In addition, because the length of wiring is long, the bit and main word lines are formed of metal wire to make the resistance as low as possible.
If the device has two polysilicon layers and two aluminum layers, for example, first and second wiring layers are formed of polysilicon on a substrate of Si while third and fourth layers are formed of aluminum. The layout is selected such that the third layer is used as bit lines and the fourth layer is used as main word lines, for example.
When the aforementioned device structure is formed, however, the following problems are raised.
On production, foreign matters such as particles enter an interlayer at which the metallic bit line layer intersects the metallic word line layer. This produces a short circuit between the bit and main word lines.
In such a type of circuit shown in FIG. 16 wherein the potential of the bit line in the stand-by state has previously been set to be always in ON state ("H" level state) through the pre-charge circuit 430, the aforementioned short circuit causes an electric current to flow from the bit lines BL to the main word line 406 since the main word line 406 and bit lines BL are respectively in "L" and "H" levels under the non-selected state.
This raises a problem in that the memory cells connected to the short-circuited bit lines and the memory cells depending on the sub word line selected by the short-circuited main word line may malfunction.
Such a malfunction can be overcome by providing a redundancy circuit. However, the main word line on question will be fixed to "L" level (non-selection state) and the bit lines will be fixed to "H" level (non-selection state). Therefore, an overcurrent of 1 mA or 2 mA, for example, due to the short circuit will continue to flow through the memory cell area through which only a reduced current of about 0.5 .mu.A normally flows. A memory cell in this state, particularly when such a memory cell is used in SRAM or the like and required to keep power consumption in a standby state as low as possible, cannot meet standard requirements for power consumption and is considered to be defective.
Such a proposal as shown in FIG. 15 has been made. FIG. 15 shows a block diagram illustrating a part of a sub row decoder in the semiconductor storage device of the prior art, which diagram is described in "A 21 mW 4 Mb CMOS SRAM for Battery Operation," ISSCC DIGEST OF TECHNICAL PAPERS March 1991:WPM3.1: pp46-47.
A system shown in FIG. 15 has a complementary pair of main word lines 410, 412, a sub word line 414 and a sub row decoder 420. The sub row decoder 420 is constructed of a p-channel transistor 424 and n-channel transistors 422, 426. The source and drain of the p-channel transistor 424 are connected parallel to those of the n-channel transistor 422. The sources are connected to the sub word line 414 while the drains are connected to one of sub row address signal lines SRAL. The gate of the n-channel transistor 422 is connected to the main word line 410 (which is selected in "H") while the gate of the n-channel transistor 426 is connected to the main word line 412 (which is selected in "L"). The source, drain and gate of the n-channel transistor 426 are connected to ground, the sub word line 414 and the main word line 412, respectively. Bit lines have been pre-charged to "H".
When the memory cell MC is in its non-selected state, the main word line 410 is in "L" state and the main word line 412 is in "H" state. Thus, the p-channel transistor 424 and the n-channel transistor 422 are off while the n-channel transistor 426 is on. Therefore, the sub word line 414 is placed in "L" through the n-channel transistor 426.
When the memory cell MC is in its selected state, the main word line 410 is in "H"; the main word line 412 is in "L"; and the sub row address signal lines SRAL are in "H". Thus, the p-channel transistor 424 and n-channel transistor 422 are turned on to make the sub word line 414 "H".
However, the system of FIG. 15 raises the following problems:
(1) Although two main word lines 410 and 412 are formed, the similar problem can be raised since a current may flow through the main word line 410 when a short circuit occurs, even if no current flows through the main word line 412.
(2) When the n-channel transistor 422 is turned on and also in its non-selected state, a signal will be transmitted from the sub row address signal lines SRAL to the sub word line 414. This causes the memory cell MC to malfunction.
(3) Providing a complementary pair of main word lines requires one more wiring layer and one more insulating interlayer. If the insulating interlayer is thin, the upper wiring layer tends to be cut due to a thickness difference between layers. If the insulating interlayer is made to be thick, a contact hole for connecting wiring layers becomes deeper, so that a contact resistance is increased. In addition, the layer thickness in the system is increased. This increases the size of a chip in the direction of thickness. Even if the two main word lines can be formed in a single layer, the area of chip required to form these main word lines will be increased. Moreover, a manufacturing cost is increased because of an increase in manufacturing time and in number of producing steps.
(4) The main word line 412 is in "L" during the time period through which the memory cell is selected. If a short circuit occurs, however, the main word line 412 will be temporarily placed in "H" by the short-circuit current. The transistor 424 will be turned off and the transistor 426 will be turned on. This lowers the potential in the sub word line so that the desired selection will not be carried out. This also raises another problem in that the other elements malfunction or are broken down.
Note that the aforementioned technical paper does not mention these problems.